FIG. 1 shows a configuration of a conventional drive circuit shown in Patent Literature 1 (Japanese Patent Publication (JP 2006-101490A)). A first power supply NVDDH and a second power supply NVDDL are connected to the drive circuit, to supply a first voltage VDDH, and a second voltage VDDL lower than the first voltage VDDH, and a ground voltage GND is also connected to the drive circuit.
The conventional drive circuit is provided with a low voltage control section 113, a level shift section 111 and a buffer section 112.
The low voltage control section 113 is connected between the second voltage NVDDL and the ground voltage GND. The low voltage control section 113 uses the third voltage VDDL as a power supply voltage.
The level shift section 111 is provided with P-channel MOS transistors MP101 and MP102, and N-channel MOS transistors MN101 and MN102. The P-channel MOS transistor MP101 and MP102 are connected with the first voltage VDDH. The N-channel MOS transistor MN101 is connected between the P-channel MOS transistor MP101 and the ground voltage GND, and a first input signal IN1 is supplied to a gate of the N-channel MOS transistor MN101. A gate of the P-channel MOS transistor MP102 is connected with a first node A101 between the P-channel MOS transistor MP101 and the N-channel MOS transistor MN101. The N-channel MOS transistor MN102 is connected between the P-channel MOS transistor MP102 and the ground voltage GND, and a second input signal IN2 is supplied to a gate of the transistor MN102. A gate of the P-channel MOS transistor MP101 is connected with a second node B101 between the P-channel MOS transistor MP102 and the N-channel MOS transistor MN102.
The buffer section 112 is provided with a push-pull output P-channel MOS transistor MP103 and a push-pull output N-channel MOS transistor MN103. The P-channel MOS transistor MP103 is connected between the first voltage VDDH and an output node OUT, and a gate thereof is connected with second node B101. The N-channel MOS transistor MN103 is connected between the output node OUT and the ground voltage GND, and a third input signal IN3 is supplied to a gate thereof.
The buffer section 112 performs a switching operation in response to a signal of the second node B101 and the third input signal IN3 from the low voltage control section 113.
FIG. 2 shows an operation in a first mode and a second mode in the conventional drive circuit.
When the signal level of the input signal IN is a high level, the low voltage control section 113 executes the first mode. The low voltage control section 113 sets signal levels of first to third input signals IN1 to IN3 to a low level, a high level and a low level in the first mode.
In this case, the N-channel MOS transistor MN102 is turned on in response to the second input signal IN2 of the high level. Simultaneously, the N-channel MOS transistor MN101 is turned off in response to the first input signal IN1 of the low level. The P-channel MOS transistor MP103 is turned on in response to a signal of the second node B101 (a second output signal) of the low level. The P-channel MOS transistor MP102 is turned off in response to a signal at the first node A101 (a first output signal) of the high level. At this time, since the voltage of the second node B101 falls to the ground voltage GND, the P-channel MOS transistor MP101 is turned on. Thus, the voltage of the output node OUT is raised to the first voltage VDDH. Also, the N-channel MOS transistor MN103 is turned off in response to the third input signal IN3 of the low level, so that the level of the input signal IN is converted and is supplied to the output node OUT.
On the other hand, when the input signal IN is in the low level, the low voltage control section 113 executes the second mode. The low voltage control section 113 sets the signal levels of the first to third input signals IN1 to IN3 to the high level, the low level and the high level in the second mode, respectively.
In this case, since the N-channel MOS transistor MN101 is turned on in response to the first input signal IN1 of the high level so that the voltage of the first node A101 falls to the ground voltage GND. The P-channel MOS transistor MP102 is turned on in response to the first output signal of the low level. Simultaneously, the N-channel MOS transistor MN102 is turned off in response to the second input signal IN2 of the low level. Thus, since the voltage of the second node B101 is raised to the first voltage VDDH, the P-channel MOS transistor MP103 is turned off. Moreover, the N-channel MOS transistor MN103 is turned on in response to the third input signal IN3 of the high level, so that the voltage of the output node OUT falls to the ground voltage GND.